Proving chaotic behaviour of CBC mode of operation

International audienceThe cipher block chaining (CBC) block cipher mode of operation was invented by IBM (International Business Machine) in 1976. It presents a very popular way of encrypting which is used in various applications. In this paper, we have mathematically proven that, under some conditions, the CBC mode of operation can admit a chaotic behaviour according to Devaney. Some cases will be properly studied in order to put in evidence this idea

A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems

The arithmetic in a finite field constitutes the core of Public Key Cryptography like RSA, ECC or pairing-based cryptography. This paper discusses an efficient hardware implementation of the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery modular multiplication combined with an effective systolic architecture designed with a Two-dimensional array of Processing Elements. The systolic architecture increases the speed of calculation by combining the concepts of pipelining and the parallel processing into a single concept. We propose the CIOS method for the Montgomery multiplication using a systolic architecture. As far as we know this is the first implementation of such design. The proposed architectures are designed for Field Programmable Gate Array platforms. They targeted to reduce the number of clock cycles of the modular multiplication. The presented implementation results of the CIOS algorithms focuses on different security levels useful in cryptography. This architecture have been designed in order to use the flexible DSP48 on Xilinx FPGAs. Our architecture is scalable and depends only on the number and size of words. For instance, we provide results of implementation for 8, 16, 32 and 64 bit long words in 33, 66, 132 and 264 clock cycles. We highlight the fact that for a given number of word, the number of clock cycles is constant

Regularized multiframe super-resolution image reconstruction using linear and nonlinear filters

The primary goal of the multiframe super-resolution image reconstruction is to produce an image with a higher resolution by integrating information extracted from a set of corresponding images with low resolution, which is used in various fields. However, super-resolution image reconstruction approaches are typically affected by annoying restorative artifacts, including blurring, noise, and staircasing effect. Accordingly, it is always difficult to balance between smoothness and edge preservation. In this paper, we intend to enhance the efficiency of multiframe super-resolution image reconstruction in order to optimize both analysis and human interpretation processes by improving the pictorial information and enhancing the automatic machine perception. As a result, we propose new approaches that firstly rely on estimating the initial high-resolution image through preprocessing of the reference low-resolution image based on median, mean, Lucy-Richardson, and Wiener filters. )is preprocessing stage is used to overcome the degradation present in the reference low-resolution image, which is a suitable kernel for producing the initial high-resolution image to be used in the reconstruction phase of the final image. then, L2 norm is employed for the data-fidelity term to minimize the residual among the predicted high-resolution image and the observed low-resolution images. Finally, bilateral total variation prior model is utilized to restrict the minimization function to a stable state of the generated HR image. )e experimental results of the synthetic data indicate that the proposed approaches have enhanced efficiency visually and quantitatively compared to other existing approaches

Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2

The Hash function has been studied by designers with the goal to improve its performances in terms of area, frequency and throughput. The Hash function is used in many embedded systems to provide security. It is become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and SHA-512 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieves good performance in term of area, frequency and throughput

High-performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication

International audienceElliptic Curve Cryptography (ECC) is becoming unavoidable, and should be used for public key protocols. It has gained increasing acceptance in practice due to the significantly smaller bit size of the operands compared to RSA for the same security level. Most protocols based on ECC imply the computation of a scalar multiplication. ECC can be performed in affine, projective, Jacobian or others models of coordinates. The arithmetic in a finite field constitutes the core of ECC Public Key Cryptography. This paper discusses an efficient hardware implementation of scalar multiplication in Jacobian coordinates by using the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery Modular Multiplication (MMM) combined with an effective systolic architecture designed with a two-dimensional array of Processing Elements (PE). As far as we know this is the first implementation of such a design for large prime fields. The proposed architectures are designed for Field Programmable Gate Array (FPGA) platforms. The objective is to reduce the number of clock cycles of the modular multiplication, which implies a good performance for ECC. The presented implementation results focuses on various security levels useful for cryptography. This architecture have been designed in order to use the flexible DSP48 on Xilinx FPGAs. Our architecture for MMM is scalable and depends only on the number and size of words

Reconfigurable Implementation of the New Secure Hash Algorithm

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An efficient and scalable modular inversion/division for public key cryptosystems

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High performance architecture of integrated protocols for encoded video application

Despite the evolution of high-speed communication network to accommodate an increasingly number of applications with diverse service requirements, there still exist a number of barriers related to the deployment of the encoded video over the ATM network. In fact, additional works have to be devoted to improve protocol architecture and to guarantee the QoS. In this paper, we first analyze the main parameters affecting the visual quality of real video pictures. Then, we define specific services to be implemented at the network interface level. We also discuss the proposed integrated protocols architecture for real time application such as video coding illustrating the function to support the challenges of managing real time services over high speed network. In fact, data cells are exposed to delays and losses, which affect the quality of the video signal. Therefore, we have to perform the adequate processing in order to keep the quality of service on an acceptable level. In this article, we propose the design of an interface between the MPEG-2 standard and the ATM network in order to improve the video visual quality. Our approach tries to overcome the difficulty imposed by traditional random cell discarding due to the bursty aspect of the traffic and the variable bit rate (VBR) transmission, nature of compressed video. The performance evaluation shows the effectiveness of the proposed interface architecture with the set of mechanisms in improving the robustness of the video delivery system